54F240/BRA

Specifications

Seated Heightmax

5.08 mm

Terminal Adımı

2.54 mm

Number Of Outputs Per Chip

8

Hts

8542.39.00.01

Package Body Material

CERAMIC, GLASS-SEALED

Risk Rank

5.07

Propagation Delay Tpd

5.5 ns

Eccn Us

EAR99

Standard Package Name

DIP

Qualification Status

Not Qualified

Power Supply Currentmax Icc

75 mA

Maximum Low Level Output Current Ma

48

Number Of Channels Per Chip

8

Lead Shape

Through Hole

Minimum Operating Supply Voltage V

4.5

Supplier Temperature Grade

Military

Üretici Parça No

54F240/BRA

Terminal Pozisyonu

DUAL

Supply Voltagemax Vsup

5.5 V

Operating Temperaturemax

125 °C

Logic Function

Buffer/Line Driver

Supplier Package

CDIP

Logic Family

F

Maximum Operating Temperature C

125

Number Of Output Enables Per Chip

2 Low

Technology

TTL

Ihs Manufacturer

NXP SEMICONDUCTORS

REACH Uyumluluk Kodu

unknown

Absolute Propagation Delay Time Ns

10.5

Pcb Changed

20

Package Style

IN-LINE

Part Life Cycle Code

Obsolete

Number Of Bits

4

Mounting

Through Hole

Load Capacitance Cl

50 pF

Propagation Delay Test Condition Pf

50

Part Package Code

DIP

Number Of Input Enables Per Chip

0

Package Description

CERAMIC, DIP-20

Bus Hold

No