74LVC1G17FS3-7-55

Specifications

Maximum Propagation Delay Time Maximum Cl Ns

6.5@5V|7@3.3V

Maximum Quiescent Current Ua

200

Number Of Input Enables Per Chip

0

Mounting

Surface Mount

Logic Function

Schmitt Trigger Buffer

Bus Hold

No

Standard Package Name

DFN

Logic Family

LVC

Number Of Outputs Per Chip

1

Tolerant Ios V

5.5 Inputs

Maximum Low Level Output Current Ma

32

Propagation Delay Test Condition Pf

50

Maximum High Level Output Current Ma

-32

Package Length

0.8

Package Height

0.28

Eccn Us

EAR99

Absolute Propagation Delay Time Ns

14

Number Of Inputs Per Chip

1

Polarity

Non-Inverting

Input Signal Type

Single-Ended

Number Of Output Enables Per Chip

0

Minimum Operating Temperature C

-40

Pcb Changed

4

Maximum Operating Temperature C

125

Ambalaj

Tape and Reel

Pin Sayısı

4

Lead Shape

No Lead

Maximum Operating Supply Voltage V

5.5

Process Technology

CMOS

Number Of Elements Per Chip

1

Parça Durumu

Active

Supplier Package

X2-DFN EP

Minimum Operating Supply Voltage V

1.65

Number Of Channels Per Chip

1

RoHS Durumu

RoHS Compliant

Typical Operating Supply Voltage V

3.3|1.8|2.5|5

Package Width

0.8